Kactus2 is a toolset to design embedded products, especially FPGA-based MP-SoCs. We aim easier IP reusabilility and practical HW/SW abstraction for easier application SW development. It is based on IEEE1685/IP-XACT XML metadata and design methodology, but extends the IP-XACT usage to upper product hierarchies and HW/SW abstraction with Multicore Association MCAPI. Kactus2 is aimed to offer easy entrance to metadata based design methodology.
Small and mid-size vendor and integrator companies that now have only the traditional toolset: office tools (doc, xls, ppt) for specification/documentation and VHDL, C/C++, and FPGA tools for designs. Kactus2 helps taking a step to metadata based design that keeps products much better manageable while still using also the familiar tools.
Universities and research laboratories that implement new content (IP bocks, SW modules). Kactus2 helps packetizing the content in a standard way for (re)using it much easier by others, specifically when the original contributor leave after e.g. a PhD project.
Bigger companies and tool providers that already have modern design tool flows and resources for developing higher abstraction methods. Kactus2 offers a great R&D environment for trying new methodology ideas and user interface innovations. We hope Kactus2 would be the well-known open reference for benchmarking other metadata-based tools.
· Quickly draft block diagram blueprints for product boards (PCB), chips, system-on-chip, IPs and get them stored in IP-XACT format
· Draft MCAPI endpoint design for all processors and fixed IPs in a product
· For new IP-blocks generate code templates (VHDL entities, headers) from IP-XACT components defined in Kactus2
· Create "electronic datasheets" of your existing IPs for library as templates and blocks ready for integration
· Import, export and integrity check IP libraries from any standard compatible IP vendor
· Create HW designs with hierarchy
· Create system designs that map SW to HW
· Create SW architecture in MCAPI communication abstraction
· Configure all designs
· Generate everything ready for HDL synthesis and SW build for all processors